65NM MIXED-SIGNAL IC
My project for Micro and Nano-Scale Electronics at the University of Guelph.
Project Summary
Designed a mixed-signal integrated circuit for a hypothetical smartwatch using a 65nm CMOS technology in Cadence Virtuoso. The integrated circuit contained an analog multiplexer, a programmable gain amplifier, and a 6-bit successive-approximation analog-to-digital converter.
Project Details
The analog multiplexer could select from three inputs based on a digital logic level provided by a digital microprocessor. The programmable gain amplifier required gains from 1 to 4 inclusive, and was implemented using an op-amp with an open circuit gain of 40 dB. The analog-to-digital converter was a 6-bit successive-approximation type with charge-redistribution topology. It took 105 samples per second with each LSB being 15.625 mV.
Project Results
The illustrations seen below are conceptual and independently created for the purpose of demonstrating the theoretical results.
Gallery
